Physical layer

The physical link will be a multi-master, (almost-)sender-only configuration. Inexpensive ICs are available that support hardening the bus sufficiently for longer distances, by using higher voltage or current levels.

The bus requires at least four wires:

• 5V
• GND
• Clock
• Data

However, due to ground offset effects it's highly recommended to use a multi-wire cable. GND should be on two or three wires. If the cable consists of twisted pairs, Clock and Data should each be paired with a GND wire, not with each other.

If you must use a 4-wire cable, one twisted pair shall be Clock/GND, the other Data/+5V.

As the CPU requires 3.3V, each board needs a small linear regulator. If more power is required, a buck converter from 12V should be used.

I²C messages self-terminate, so there is no length byte.

Link layer

I²C does not carry a dedicated source address, thus the first byte (or two) will be the sender's I²C address.

The master's address is fixed at x08; unassigned slaves shall use x09 as their origin. However, unassigned slaves are not addressed directly, as they use a read-after-write cycle to obtain their address.